ICALEPCS2017 - List of Authors (Kim, K.H.)

Paper	Title	Page
TUMPL04	LCLS-II Timing Pattern Generator Configuration GUIs	307
	C. Bianchini, J. Browne, K.H. Kim, P. Krejcik, M. Weaver, S. Zelazny SLAC, Menlo Park, California, USA
	The LINAC Coherent Light Source II (LCLS-II) is an upgrade of the SLAC National Accelerator Laboratory LCLS facility to a superconducting LINAC with multiple destinations at different power levels. The challenge in delivering timing to a superconducting LINAC is dictated by the stability requirements for the beam power and the 1MHz rate. A timing generator will produce patterns instead of events because of the large number of event codes required. The poster explains how the stability requirements are addressed by the design of two Graphical User Interfaces (GUI). The Allow Table GUI filters the timing pattern requests respecting the Machine Protection System (MPS) defined Power Class and the electron beam dump capacities. The Timing Pattern Generator (TPG) programs Sequence Engines to deliver the beam rate configuration requested by the user. The low level program, The TPG generates the patterns, which contains the timing information propagated to the Timing Pattern Receiver (TPR). Both are implemented with an FPGA solution and configured by EPICS. The poster shows an overall design of the high-level software solutions that meet the physics requirements for LCLS-II timing.
	Slides TUMPL04 [1.030 MB]
	Poster TUMPL04 [0.883 MB]
DOI •	reference for this paper ※ https://doi.org/10.18429/JACoW-ICALEPCS2017-TUMPL04
Export •	reference for this paper using ※ BibTeX, ※ LaTeX, ※ Text/Word, ※ RIS, ※ EndNote (xml)

THPHA138	YCPSWASYN: EPICS Driver for FPGA Register Access and Asynchronous Messaging	1707
	J.A. Vásquez, J.M. D'Ewart, K.H. Kim, T. Straumann, E. Williams SLAC, Menlo Park, California, USA
	The Linac Coherent Light Source II (LCLS-II) is a major upgrade of the LCLS facility at SLAC, scheduled to start operations in 2020. The High Performance Systems (HPS) defines a set of LCLS-II controls sub-systems which are directly impacted by its 1 MHz operation. It is formed around a few key concepts: ATCA based packaging, digital and analog application boards, and 10G Ethernet based interconnections for controls. The Common Platform provides the common parts of the HPS in term of hardware, firmware, and software. The Common Platform Software (CPSW) provides a standardized interface to the common platform's FPGA for all high-level software. YAML is used to define the hardware topology and all necessary parameters. YCPSWASYN is an asynPortDriver based EPICS module for FPGA register access and asynchronous messaging using CPSW. YCPSWSYN has two operation modes: an automatic mode where PVs are automatically created for all registers and the record's fields are populated with information found in YAML; and a manual mode where the engineer can choose which register to expose via PVs and freely choose the record's filed information.
	Poster THPHA138 [1.189 MB]
DOI •	reference for this paper ※ https://doi.org/10.18429/JACoW-ICALEPCS2017-THPHA138
Export •	reference for this paper using ※ BibTeX, ※ LaTeX, ※ Text/Word, ※ RIS, ※ EndNote (xml)

Paper

Title

Page

LCLS-II Timing Pattern Generator Configuration GUIs

307

C. Bianchini, J. Browne, K.H. Kim, P. Krejcik, M. Weaver, S. Zelazny
SLAC, Menlo Park, California, USA

The LINAC Coherent Light Source II (LCLS-II) is an upgrade of the SLAC National Accelerator Laboratory LCLS facility to a superconducting LINAC with multiple destinations at different power levels. The challenge in delivering timing to a superconducting LINAC is dictated by the stability requirements for the beam power and the 1MHz rate. A timing generator will produce patterns instead of events because of the large number of event codes required. The poster explains how the stability requirements are addressed by the design of two Graphical User Interfaces (GUI). The Allow Table GUI filters the timing pattern requests respecting the Machine Protection System (MPS) defined Power Class and the electron beam dump capacities. The Timing Pattern Generator (TPG) programs Sequence Engines to deliver the beam rate configuration requested by the user. The low level program, The TPG generates the patterns, which contains the timing information propagated to the Timing Pattern Receiver (TPR). Both are implemented with an FPGA solution and configured by EPICS. The poster shows an overall design of the high-level software solutions that meet the physics requirements for LCLS-II timing.

Slides TUMPL04 [1.030 MB]

Poster TUMPL04 [0.883 MB]

DOI •

reference for this paper ※ https://doi.org/10.18429/JACoW-ICALEPCS2017-TUMPL04

Export •

reference for this paper using ※ BibTeX, ※ LaTeX, ※ Text/Word, ※ RIS, ※ EndNote (xml)

THPHA138

YCPSWASYN: EPICS Driver for FPGA Register Access and Asynchronous Messaging

1707

J.A. Vásquez, J.M. D'Ewart, K.H. Kim, T. Straumann, E. Williams
SLAC, Menlo Park, California, USA

The Linac Coherent Light Source II (LCLS-II) is a major upgrade of the LCLS facility at SLAC, scheduled to start operations in 2020. The High Performance Systems (HPS) defines a set of LCLS-II controls sub-systems which are directly impacted by its 1 MHz operation. It is formed around a few key concepts: ATCA based packaging, digital and analog application boards, and 10G Ethernet based interconnections for controls. The Common Platform provides the common parts of the HPS in term of hardware, firmware, and software. The Common Platform Software (CPSW) provides a standardized interface to the common platform's FPGA for all high-level software. YAML is used to define the hardware topology and all necessary parameters. YCPSWASYN is an asynPortDriver based EPICS module for FPGA register access and asynchronous messaging using CPSW. YCPSWSYN has two operation modes: an automatic mode where PVs are automatically created for all registers and the record's fields are populated with information found in YAML; and a manual mode where the engineer can choose which register to expose via PVs and freely choose the record's filed information.

Poster THPHA138 [1.189 MB]

DOI •

reference for this paper ※ https://doi.org/10.18429/JACoW-ICALEPCS2017-THPHA138

Export •

reference for this paper using ※ BibTeX, ※ LaTeX, ※ Text/Word, ※ RIS, ※ EndNote (xml)