Author: Alverson, S.C.
Paper Title Page
THPHA024 SLAC Klystron Test Lab Bake Station Upgrade 1393
 
  • S.C. Alverson, P. Bellomo, K.J. Mattison
    SLAC, Menlo Park, California, USA
 
  Funding: SLAC National Accelerator Lab
The Klystron Bake Station at SLAC is a facility for baking out klystrons (high power RF amplifiers) among other equipment in preparation for installation in the linac. The scope of this project was to upgrade the 30 year old controls (based on VMS and CAMAC) to utilize PLC automation and an EPICS user interface. The new system allows for flexible configuration of the bake out schedule which can be saved to files or edited real time both through an EPICS soft IOC as well as a local touch panel HMI. Other improvements include active long term archiving of all data, COTS hardware (replacing custom-built CAMAC cards), email notification of fault states, and graphical user interfaces (old system was command line only). The first station upgraded came online in November 2016 and two more stations are planned to follow this year. Year poster discusses the improvements made and problems encountered in performing the upgrade.
 
poster icon Poster THPHA024 [2.555 MB]  
DOI • reference for this paper ※ https://doi.org/10.18429/JACoW-ICALEPCS2017-THPHA024  
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THPHA025 LCLS-II Injector Laser System 1397
 
  • S.C. Alverson, D.E. Anderson, S. Gilevich
    SLAC, Menlo Park, California, USA
 
  Funding: SLAC National Accelerator Lab - LCLS-II
The Linac Coherent Light Source II (LCLSII) is a new Free Electron Laser (FEL) facility being built as an upgrade to the existing LCLS-I and is planned for early commissioning this year (2017) and full operation in 2020. The injector laser which hits the cathode to produce the electrons for this FEL source is conceptually similar to LCLS-I, but will utilize an upgraded controls architecture in order to be compatible with the faster repetition rate (1 MHz) of the beam. This includes moving to industrial PCs from VME and utilizing SLAC designed PCIe timing cards and camera framegrabbers. This poster discusses the overall architecture planned for this installation and discusses the reasoning behind the choices of hardware and control scheme.
 
poster icon Poster THPHA025 [1.381 MB]  
DOI • reference for this paper ※ https://doi.org/10.18429/JACoW-ICALEPCS2017-THPHA025  
Export • reference for this paper using ※ BibTeX, ※ LaTeX, ※ Text/Word, ※ RIS, ※ EndNote (xml)