Present and Future of Harmony Bus, a Real-Time High Speed Bus for Data Transfer Between FPGA Cores

Broseta, Manuel; Avila-Abellan, Jose; Blanch-TornÃ©, Sergi; Cuní, Guifre; Fernández-Carreiras, David; Matilla, Oscar; Rodriguez, Marc; Salabert, Jordi; Serra-Gallifa, Xavier

doi:10.18429/JACoW-ICALEPCS2017-WEAPL01

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RIS citation export for WEAPL01: Present and Future of Harmony Bus, a Real-Time High Speed Bus for Data Transfer Between FPGA Cores

TY - CONF
AU - Broseta, M.
AU - Avila-Abellan, J.A.
AU - Blanch-TornÃ©, S.
AU - Cuní, G.
AU - Fernández-Carreiras, D.
AU - Matilla, O.
AU - Rodriguez, M.
AU - Salabert, J.
AU - Serra-Gallifa, X.
ED - Schaa, Volker RW
ED - Costa, Isidre
ED - FernÃ¡ndez, David
ED - Matilla, Ãscar
TI - Present and Future of Harmony Bus, a Real-Time High Speed Bus for Data Transfer Between FPGA Cores
J2 - Proc. of ICALEPCS2017, Barcelona, Spain, 8-13 October 2017
C1 - Barcelona, Spain
T2 - International Conference on Accelerator and Large Experimental Control Systems
T3 - 16
LA - english
AB - When feedback loops latencies shall be lower than milliseconds range the performance of FPGA-based solutions are unrivaled. One of the main difficulties in these solutions is how to make compatible a full custom digital design with a generic interface and the high-level control software. ALBA simplified the development process of electronic instrumentation with the use of Harmony Bus (HB)*. Based on the Self-Describing Bus, developed at CERN/GSI, it creates a bus framework where different modules share timestamped data and generate events. This solution enables the high-level control software in a Single Board Computer or PC, to easily configure the expected functionally in the FPGA and manage the real-time data acquired. This framework has been already used in the new Em# electrometer**, produced within a collaboration between ALBA and MAXIV, that is currently working in both synchrotrons. Future plans include extending the FPGA cores library, high-level functions and the development of a new auto-generation tool able to dynamically create the FPGA configuration file simplifying the development process of new functionalities.
PB - JACoW
CP - Geneva, Switzerland
SP - 1012
EP - 1016
KW - ion
KW - FPGA
KW - software
KW - feedback
KW - controls
DA - 2018/01
PY - 2018
SN - 978-3-95450-193-9
DO - 10.18429/JACoW-ICALEPCS2017-WEAPL01
UR - http://jacow.org/icalepcs2017/papers/weapl01.pdf
ER -