The Joint Accelerator Conferences Website (JACoW) is an international collaboration that publishes the proceedings of accelerator conferences held around the world.
TY - CONF AU - Hill, J.O. ED - Corvetti, Lou ED - Riches, Kathleen ED - Schaa, Volker RW TI - The LASNCE FPGA Embedded Signal Processing Framework J2 - Proc. of ICALEPCS2015, Melbourne, Australia, 17-23 October 2015 C1 - Melbourne, Australia T2 - International Conference on Accelerator and Large Experimental Physics Control Systems T3 - 15 LA - english AB - During the replacement of some LANSCE LINAC instrumentation systems a common architecture for timing system synchronized embedded signal processing systems was developed. The design follows trends of increasing levels of electronics system integration; a single commercial-off-the-shelf (COTS) board assumes the roles of analog-to-digital conversion and advanced signal processing while also providing the LAN attached EPICS IOC functionality. These systems are based on agile FPGA-based COTS VITA VPX boards with an VITA FMC mezzanine site. The signal processing is primarily developed at a high level specifying numeric algorithms in software source code to be integrated together with COTS signal processing intellectual property components for synthesis of hardware implementations. This paper will discuss the requirements, the decision point selecting the VPX together with the FMC industry standards, the benefits along with costs of system integrating multi-vendor COTS components, the design of some of the signal processing algorithms, and the benefits along with costs of embedding the EPICS IOC within an FPGA. PB - JACoW CP - Geneva, Switzerland SP - 1079 EP - 1082 KW - FPGA KW - framework KW - software KW - hardware KW - interface DA - 2015/12 PY - 2015 SN - 978-3-95450-148-9 DO - 10.18429/JACoW-ICALEPCS2015-THHA2O02 UR - http://jacow.org/icalepcs2015/papers/thha2o02.pdf ER -