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RIS citation export for TUAPP01: Hardware-in-the-Loop Testing of Accelerator Firmware

TY  - CONF
AU  - Serrano, C.
AU  - Betz, M.
AU  - Doolittle, L.R.
AU  - Paiagua, S.
AU  - Vytla, V.K.
ED  - White, Karen S.
ED  - Brown, Kevin A.
ED  - Dyer, Philip S.
ED  - Schaa, Volker RW
TI  - Hardware-in-the-Loop Testing of Accelerator Firmware
J2  - Proc. of ICALEPCS2019, New York, NY, USA, 05-11 October 2019
CY  - New York, NY, USA
T2  - International Conference on Accelerator and Large Experimental Physics Control Systems
T3  - 17
LA  - english
AB  - Continuous Integration (CI) is widely used in industry, especially in the software world. Here we propose a combination of CI processes to run firmware and software tests both in simulation and on real hardware that can be well adapted to FPGA-based accelerator electronics designs. We have built a test rack with a variety of hardware platforms. Relying on source code version control tools, when a developer submits a change to the code base, a multi-stage test pipeline is triggered. Unit tests are run automatically, bitstreams are generated for the various supported FPGA platforms and loaded onto the FPGAs in the rack, and tests are run on hardware. Reports are generated upon test completion and notifications are sent to the developers in case of failure.
PB  - JACoW Publishing
CP  - Geneva, Switzerland
SP  - 659
EP  - 664
KW  - software
KW  - hardware
KW  - controls
KW  - FPGA
KW  - LLRF
DA  - 2020/08
PY  - 2020
SN  - 2226-0358
SN  - 978-3-95450-209-7
DO  - doi:10.18429/JACoW-ICALEPCS2019-TUAPP01
UR  - https://jacow.org/icalepcs2019/papers/tuapp01.pdf
ER  -