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@InProceedings{serrano:icalepcs2019-tuapp01,
author = {C. Serrano and M. Betz and L.R. Doolittle and S. Paiagua and V.K. Vytla},
title = {{Hardware-in-the-Loop Testing of Accelerator Firmware}},
booktitle = {Proc. ICALEPCS'19},
pages = {659--664},
paper = {TUAPP01},
language = {english},
keywords = {software, hardware, controls, FPGA, LLRF},
venue = {New York, NY, USA},
series = {International Conference on Accelerator and Large Experimental Physics Control Systems},
number = {17},
publisher = {JACoW Publishing, Geneva, Switzerland},
month = {08},
year = {2020},
issn = {2226-0358},
isbn = {978-3-95450-209-7},
doi = {10.18429/JACoW-ICALEPCS2019-TUAPP01},
url = {https://jacow.org/icalepcs2019/papers/tuapp01.pdf},
note = {https://doi.org/10.18429/JACoW-ICALEPCS2019-TUAPP01},
abstract = {Continuous Integration (CI) is widely used in industry, especially in the software world. Here we propose a combination of CI processes to run firmware and software tests both in simulation and on real hardware that can be well adapted to FPGA-based accelerator electronics designs. We have built a test rack with a variety of hardware platforms. Relying on source code version control tools, when a developer submits a change to the code base, a multi-stage test pipeline is triggered. Unit tests are run automatically, bitstreams are generated for the various supported FPGA platforms and loaded onto the FPGAs in the rack, and tests are run on hardware. Reports are generated upon test completion and notifications are sent to the developers in case of failure.},
}