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BiBTeX citation export for TUPP09: Multiplexer System for the SPEAR3 Booster BPM Upgrade

@InProceedings{toufexis:ibic2020-tupp09,
  author       = {F. Toufexis and P. Boussina and L. Campana and W.J. Corbett and J.J. Sebek},
  title        = {{Multiplexer System for the SPEAR3 Booster BPM Upgrade}},
  booktitle    = {Proc. IBIC'20},
  pages        = {41--45},
  paper        = {TUPP09},
  language     = {english},
  keywords     = {booster, controls, interface, synchrotron, ISOL},
  venue        = {Santos, Brazil},
  series       = {International Beam Instrumentation Conference},
  number       = {9},
  publisher    = {JACoW Publishing, Geneva, Switzerland},
  month        = {10},
  year         = {2020},
  issn         = {2673-5350},
  isbn         = {978-3-95450-222-6},
  doi          = {10.18429/JACoW-IBIC2020-TUPP09},
  url          = {https://www.jacow.org/ibic2020/papers/tupp09.pdf},
  note         = {https://doi.org/10.18429/JACoW-IBIC2020-TUPP09},
  abstract     = {BPM measurements in booster synchrotrons are often only critical during accelerator commissioning or when a problem occurs. As a result, many facilities do not make large investments in booster BPM signal processors; they either have very few BPMs and/or use older generation processors. The SPEAR3 booster BPM processor system, for instance, has operated since 1990 with commercial multiplexers to switch between BPM button signals into a single dated analog BPM processor that was developed at SLAC*. This system has reached its end-of-life so we are in the process of upgrading to modern multiplexers that feed a pair of turn-by-turn Libera SPARK-ERXR processors. This low-cost solution gives us the ability to arbitrarily multiplex between BPM signals during the energy ramp with modern BPM processors. The system can either measure 2 BPMs turn-by-turn in parallel during the entire energy ramp, or sequentially measure all BPMs (2 at a time) at different time slices within the ramp. Here we show measurements of the MiniCircuits switch we chose as well as our architecture for the upgrade.},
}