IBIC2018 - List of Authors (Marjanovic, J.)

Paper	Title	Page
THOA01	Low vs High Level Programming for FPGA	527
	J. Marjanovic DESY, Hamburg, Germany
	From their introduction in the eighties, Field-Programmable Gate Arrays (FPGAs) have grown in size and performance for several orders of magnitude. As the FPGA capabilities have grown, so have the designs. It seems that current tools and languages (VHDL and (System)Verilog) do not match the complexity required for advanced digital signal processing (DSP) systems usually found in experimental physics applications. In the last couple of years several commercial High-Level Synthesis (HLS) tools have emerged, providing a new method to implement FPGA designs, or at least some parts of it. By providing a higher level of abstraction, new tools offer a possibility to express algorithms in a way which is closer to the mathematical description. Such implementation is understood by a broader range of people, and thus minimizes the documentation and communication issues. Several examples of DSP algorithms relevant for beam instrumentation will be presented. Implementations of these algorithms with different HLS tools and traditional implementation in VHDL will be compared.
	Slides THOA01 [1.873 MB]
DOI •	reference for this paper ※ https://doi.org/10.18429/JACoW-IBIC2018-THOA01
About •	paper received ※ 04 September 2018 paper accepted ※ 12 September 2018 issue date ※ 29 January 2019
Export •	reference for this paper using ※ BibTeX, ※ LaTeX, ※ Text/Word, ※ RIS, ※ EndNote (xml)

THOA02	High-Speed Direct Sampling FMC for Beam Diagnostic and Accelerator Protection Applications	534
	J. Zink, M.K. Czwalinna, M. Fenner, S. Jabłoński, J. Marjanovic, H. Schlarb DESY, Hamburg, Germany
	The rapid development in the field of digitizers is leading to Analog-to-Digital Converters (ADC) with ever higher sampling rates. Nowadays many high-speed digitizers for RF applications and radio communication are available, which can sample broadband signals, without the need of down converters. These ADCs fit perfectly into beam instrumentation and diagnostic applications, e.g. Bunch Arrival time Monitor (BAM), klystron life-time management or continuous wave synchronization. To cover all these high-frequency diagnostic applications, DESY has developed a direct sampling FMC digitizer board based on a high-speed ADC with an analog input bandwidth of 2.7 GHz. A high-speed data acquisition system capable of acquiring 2 channels at 800 MSP/s will be presented. As first model application of the versatile digitizer board is the coarse bunch arrival time diagnostics in the free electron laser FLASH at DESY.
	Slides THOA02 [5.817 MB]
DOI •	reference for this paper ※ https://doi.org/10.18429/JACoW-IBIC2018-THOA02
About •	paper received ※ 04 September 2018 paper accepted ※ 13 September 2018 issue date ※ 29 January 2019
Export •	reference for this paper using ※ BibTeX, ※ LaTeX, ※ Text/Word, ※ RIS, ※ EndNote (xml)

Paper

Title

Page

Low vs High Level Programming for FPGA

527

J. Marjanovic
DESY, Hamburg, Germany

From their introduction in the eighties, Field-Programmable Gate Arrays (FPGAs) have grown in size and performance for several orders of magnitude. As the FPGA capabilities have grown, so have the designs. It seems that current tools and languages (VHDL and (System)Verilog) do not match the complexity required for advanced digital signal processing (DSP) systems usually found in experimental physics applications. In the last couple of years several commercial High-Level Synthesis (HLS) tools have emerged, providing a new method to implement FPGA designs, or at least some parts of it. By providing a higher level of abstraction, new tools offer a possibility to express algorithms in a way which is closer to the mathematical description. Such implementation is understood by a broader range of people, and thus minimizes the documentation and communication issues. Several examples of DSP algorithms relevant for beam instrumentation will be presented. Implementations of these algorithms with different HLS tools and traditional implementation in VHDL will be compared.

Slides THOA01 [1.873 MB]

DOI •

reference for this paper ※ https://doi.org/10.18429/JACoW-IBIC2018-THOA01

About •

paper received ※ 04 September 2018 paper accepted ※ 12 September 2018 issue date ※ 29 January 2019

Export •

reference for this paper using ※ BibTeX, ※ LaTeX, ※ Text/Word, ※ RIS, ※ EndNote (xml)

THOA02

High-Speed Direct Sampling FMC for Beam Diagnostic and Accelerator Protection Applications

534

J. Zink, M.K. Czwalinna, M. Fenner, S. Jabłoński, J. Marjanovic, H. Schlarb
DESY, Hamburg, Germany

The rapid development in the field of digitizers is leading to Analog-to-Digital Converters (ADC) with ever higher sampling rates. Nowadays many high-speed digitizers for RF applications and radio communication are available, which can sample broadband signals, without the need of down converters. These ADCs fit perfectly into beam instrumentation and diagnostic applications, e.g. Bunch Arrival time Monitor (BAM), klystron life-time management or continuous wave synchronization. To cover all these high-frequency diagnostic applications, DESY has developed a direct sampling FMC digitizer board based on a high-speed ADC with an analog input bandwidth of 2.7 GHz. A high-speed data acquisition system capable of acquiring 2 channels at 800 MSP/s will be presented. As first model application of the versatile digitizer board is the coarse bunch arrival time diagnostics in the free electron laser FLASH at DESY.

Slides THOA02 [5.817 MB]

DOI •

reference for this paper ※ https://doi.org/10.18429/JACoW-IBIC2018-THOA02

About •

paper received ※ 04 September 2018 paper accepted ※ 13 September 2018 issue date ※ 29 January 2019

Export •

reference for this paper using ※ BibTeX, ※ LaTeX, ※ Text/Word, ※ RIS, ※ EndNote (xml)