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https://doi.org/10.18429/JACoW-ICALEPCS2017-TUPHA168
Title Improving Throughput and Latency of D-Bus to Meet the Requirements of the Fair Control System
Authors
  • D.S. Day, A. Hahn, C. Prados, M. Reese
    GSI, Darmstadt, Germany
Abstract In developing the control system for the FAIR accelerator complex we encountered strict latency and throughput contraints on the timely supply of data to devices controlling ramped magnets. In addition, the timing hardware that interfaces to the White Rabbit timing network may be shared by multiple processes on a single front-end computer. This paper describes the interprocess communication and resource-sharing system, and the consequences of using the D-Bus message bus. Then our experience of improving latency and throughput performance to meet the realtime requirements of the control system is discussed. Work is also presented on prioritisation techniques to allow time-critical services to share the bus with other components.
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Conference ICALEPCS2017, Barcelona, Spain
Series International Conference on Accelerator and Large Experimental Control Systems (16th)
Proceedings Link to full ICALEPCS2017 Proccedings
Session Poster Session
Date 10-Oct-17   16:45–19:00
Main Classification Software Technology Evolution
Keywords ion, timing, hardware, software, controls
Publisher JACoW, Geneva, Switzerland
Editors Volker RW Schaa (GSI, Darmstadt, Germany); Isidre Costa (ALBA-CELLS, Cerdanyola del Vallès, Spain); David Fernández (ALBA-CELLS, Cerdanyola del Vallès, Spain); Óscar Matilla (ALBA-CELLS, Cerdanyola del Vallès, Spain)
ISBN 978-3-95450-193-9
Published January 2018
Copyright
Copyright © 2018 by JACoW, Geneva, Switzerland     CC-BY Creative Commons License
cc Creative Commons Attribution 3.0