TUBAU —  Hardware   (11-Oct-11   10:45—12:30)
Chair: K. Rehlich, DESY, Hamburg, Germany
Paper Title Page
TUBAUST01 FPGA-based Hardware Instrumentation Development on MAST 544
  • B.K. Huang, R.M. Myers, R.M. Sharples
    Durham University, Durham, United Kingdom
  • N. Ben Ayed, G. Cunningham, A. Field, S. Khilar, G.A. Naylor
    CCFE, Abingdon, Oxon, United Kingdom
  • R.G.L. Vann
    York University, Heslington, York, United Kingdom
  Funding: This work was part-funded by the RCUK Energy Programme under grant EP/I501045 and the European Communities under the Contract of Association between EURATOM and CCFE.
On MAST (the Mega Amp Spherical Tokamak) at Culham Centre for Fusion Energy some key control systems and diagnostics are being developed and upgraded with FPGA hardware. FPGAs provide many benefits including low latency and real-time digital signal processing. FPGAs blur the line between hardware and software. They are programmed (in VHDL/Verilog language) using software, but once configured act deterministically as hardware. The challenges in developing a system are keeping up-front and maintenance costs low, and prolonging the life of the device as much as possible. We accomplish lower costs by using industry standards such as the FMC (FPGA Mezzanine Card) Vita 57 standard and by using COTS (Commercial Off The Shelf) components which are significantly less costly than developing them in-house. We extend the device operational lifetime by using a flexible FPGA architecture and industry standard interfaces. We discuss the implementation of FPGA control on two specific systems on MAST. The Vertical Stabilisation system comprises of a 1U form factor box with 1 SP601 Spartan6 FPGA board, 10/100 Ethernet access, Microblaze processor, 24-bit σ delta ADS1672 ADC and ATX power supply for remote power cycling. The Electron Bernstein Wave system comprises of a 4U form factor box with 2 ML605 Virtex6 FPGA boards, Gigabit Ethernet, Microblaze processor and 2 FMC108 ADC providing 16 Channels with 14-bit at 250MHz. AXI4 is used as the on chip bus between firmware components to allow very high data rates which has been tested at over 40Gbps streaming into a 2GB DDR3 SODIMM.
slides icon Slides TUBAUST01 [8.172 MB]  
TUBAUST02 FPGA Communications Based on Gigabit Ethernet 547
  • L.R. Doolittle, C. Serrano
    LBNL, Berkeley, California, USA
  The use of Field Programmable Gate Arrays (FPGAs) in accelerators is widespread due to their flexibility, performance, and affordability. Whether they are used for fast feedback systems, data acquisition, fast communications using custom protocols, or any other application, there is a need for the end-user and the global control software to access FPGA features using a commodity computer. The choice of communication standards that can be used to interface to a FPGA board is wide, however there is one that stands out for its maturity, basis in standards, performance, and hardware support: Gigabit Ethernet. In the context of accelerators it is desirable to have highly reliable, portable, and flexible solutions. We have therefore developed a chip- and board-independent FPGA design which implements the Gigabit Ethernet standard. Our design has been configured for use with multiple projects, supports full line-rate traffic, and communicates with any other device implementing the same well-established protocol, easily supported by any modern workstation or controls computer.  
slides icon Slides TUBAUST02 [0.909 MB]  
TUBAULT03 The Upgrade Path from Legacy VME to VXS Dual Star Connectivity for Large Scale Data Acquisition and Trigger Systems 550
  • C. Cuevas, D. Abbott, F.J. Barbosa, H. Dong, W. Gu, E. Jastrzembski, S.R. Kaneta, B. Moffit, N. Nganga, B.J. Raydo, A. Somov, W.M. Taylor, J. Wilson
    JLAB, Newport News, Virginia, USA
  Funding: Authored by Jefferson Science Associates, LLC under U.S. DOE Contract No. DE-AC05-06OR23177
New instrumentation modules have been designed by Jefferson Lab and to take advantage of the higher performance and elegant backplane connectivity of the VITA 41 VXS standard. These new modules are required to meet the 200KHz trigger rates envisioned for the 12GeV experimental program. Upgrading legacy VME designs to the high speed gigabit serial extensions that VXS offers, comes with significant challenges, including electronic engineering design, plus firmware and software development issues. This paper will detail our system design approach including the critical system requirement stages, and explain the pipeline design techniques and selection criteria for the FPGA that require embedded Gigabit serial transceivers. The entire trigger system is synchronous and operates at 250MHz clock with synchronization signals, and the global trigger signals distributed to each front end readout crate via the second switch slot in the 21 slot, dual star VXS backplane. The readout of the buffered detector signals relies on 2eSST over the standard VME64x path at >200MB/s. We have achieved 20Gb/s transfer rate of trigger information within one VXS crate and will present results using production modules in a two crate test configuration with both VXS crates fully populated. The VXS trigger modules that reside in the front end crates, will be ready for production orders by the end of the 2011 fiscal year. VXS Global trigger modules are in the design stage now, and will be complete to meet the installation schedule for the 12GeV Physics program.
slides icon Slides TUBAULT03 [7.189 MB]  
TUBAULT04 Open Hardware for CERN’s Accelerator Control Systems 554
  • E. Van der Bij, P. Alvarez, M. Ayass, A. Boccardi, M. Cattin, C. Gil Soriano, E. Gousiou, S. Iglesias Gonsálvez, G. Penacoba Fernandez, J. Serrano, N. Voumard, T. Włostowski
    CERN, Geneva, Switzerland
  The accelerator control systems at CERN will be renovated and many electronics modules will be redesigned as the modules they will replace cannot be bought anymore or use obsolete components. The modules used in the control systems are diverse: analog and digital I/O, level converters and repeaters, serial links and timing modules. Overall around 120 modules are supported that are used in systems such as beam instrumentation, cryogenics and power converters. Only a small percentage of the currently used modules are commercially available, while most of them had been specifically designed at CERN. The new developments are based on VITA and PCI-SIG standards such as FMC (FPGA Mezzanine Card), PCI Express and VME64x using transition modules. As system-on-chip interconnect, the public domain Wishbone specification is used. For the renovation, it is considered imperative to have for each board access to the full hardware design and its firmware so that problems could quickly be resolved by CERN engineers or its collaborators. To attract other partners, that are not necessarily part of the existing networks of particle physics, the new projects are developed in a fully 'Open' fashion. This allows for strong collaborations that will result in better and reusable designs. Within this Open Hardware project new ways of working with industry are being tested with the aim to prove that there is no contradiction between commercial off-the-shelf products and openness and that industry can be involved at all stages, from design to production and support.  
slides icon Slides TUBAULT04 [7.225 MB]  
TUBAUIO05 Challenges for Emerging New Electronics Standards for Physics 558
  • R.S. Larsen
    SLAC, Menlo Park, California, USA
  Funding: Work supported by US Department of Energy Contract DE AC03 76SF00515
A unique effort is underway between industry and the international physics community to extend the Telecom industry’s Advanced Telecommunications Computing Architecture (ATCA and MicroTCA) to meet future needs of the physics machine and detector community. New standard extensions for physics have now been designed to deliver unprecedented performance and high subsystem availability for accelerator controls, instrumentation and data acquisition. Key technical features include a unique out-of-band imbedded standard Intelligent Platform Management Interface (IPMI) system to manage hot-swap module replacement and hardware-software failover. However the acceptance of any new standard depends critically on the creation of strong collaborations among users and between user and industry communities. For the relatively small high performance physics market to attract strong industry support requires collaborations to converge on core infrastructure components including hardware, timing, software and firmware architectures; as well as to strive for a much higher degree of interoperability of both lab and industry designed hardware-software products than past generations of standards. The xTCA platform presents a unique opportunity for future progress. This presentation will describe status of the hardware-software extension plans; technology advantages for machine controls and data acquisition systems; and examples of current collaborative efforts to help develop an industry base of generic ATCA and MicroTCA products in an open-source environment.
1. PICMG, the PCI Industrial Computer Manufacturer’s Group
2. Lab representation on PICMG includes CERN, DESY, FNAL, IHEP, IPFN, ITER and SLAC
slides icon Slides TUBAUIO05 [1.935 MB]